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PIC18F1230/1330

DS39758D-page 164

2009 Microchip Technology Inc.

15.3

EUSART Synchronous

Master Mode

The Master mode indicates that the processor trans-

mits the master clock on the CK line. The Synchronous

Master mode is entered by setting the CSRC bit

(TXSTA<7>). In this mode, the data is transmitted in a

half-duplex manner (i.e., transmission and reception do

not occur at the same time). When transmitting data,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit SYNC (TXSTA<4>). In

addition, enable bit, SPEN (RCSTA<7>), is set in order

to configure the TX and RX pins to CK (clock) and DT

(data) lines, respectively.

The Master mode indicates that the processor

transmits the master clock on the CK line. Clock

polarity is selected with the SCKP bit (BAUDCON<4>).

Setting SCKP sets the Idle state on CK as high, while

clearing the bit sets the Idle state as low.

15.3.1

EUSART SYNCHRONOUS MASTER

TRANSMISSION

The EUSART transmitter block diagram is shown in

Figure 15-3. The heart of the transmitter is the Transmit

(Serial) Shift Register (TSR). The Shift register obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available).

Once the TXREG register transfers the data to the TSR

the TXIF flag bit (PIR1<4>) is set. The interrupt can be

enabled or disabled by setting or clearing the interrupt

enable bit, TXIE (PIE1<4>). TXIF is set regardless of

the state of enable bit, TXIE; it cannot be cleared in

software. It will reset only when new data is loaded into

the TXREG register.

While flag bit TXIF indicates the status of the TXREG

status of the TSR register. TRMT is a read-only bit which

is set when the TSR is empty. No interrupt logic is tied to

this bit so the user has to poll this bit in order to

determine if the TSR register is empty. The TSR is not

mapped in data memory so it is not available to the user.

To set up a Synchronous Master Transmission:

Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRG16

bit, as required, to achieve the desired baud rate.

Enable the synchronous master serial port by

setting bits, SYNC, SPEN and CSRC.

If interrupts are desired, set enable bit, TXIE.

If 9-bit transmission is desired, set bit, TX9.

Enable the transmission by setting bit, TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit, TX9D.

Start transmission by loading data to the TXREG

If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 15-11:

SYNCHRONOUS TRANSMISSION

bit 0

bit 1

bit 7

Word 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

bit 2

bit 0

bit 1

bit 7

RA3/RX/DT

RA2/TX/CK pin

Write to

TXREG Reg

TXIF bit

(Interrupt Flag)

TXEN bit ‘1’

‘1’

Word 2

TRMT bit

Note:

Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

( = 0)

Write Word 2

Write Word 1

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